ENBIS: European Network for Business and Industrial Statistics

Statistical Challenges and Opportunities in Timing Analysis of

21 September 2009, 16:05 – 16:25

Abstract

Submitted by

Alessandro Di Bucchianico

Authors

A. Di Bucchianico

Affiliation

Laboratory for Industrial Mathematics Eindhoven

Abstract

Device and interconnect dimensions in nanometer silicon
technologies have reached such small values it is becoming
increasingly difficult to control process and environmental
conditions. Therefore variability (both inter-die and
intra-die) can no longer be ignored in chip design and
probabilistic and statistical methods must be used instead of
deterministic methods. In particular this holds for static
timing analysis, a widely used sign-off tool in chip design for
timing analysis. The main emphasis in Statistical Static Timing
Analysis has been on probabilistic aspects, in particular in
the design of algorithms to efficiently compute delay
distributions which involves summing and taking maxima of a
large number of random variables. We will give an overview of
the state-of-the art concerning statistical issues and point
the challenges and opportunities in this direction.

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